Lecture 5 - Counters

Asynchronous ripple counter

This one is easy to implement and understand, but the outputs do not all change simultaneously. It takes some finite time for transistors to change state, and thus for each flipflop to alter its output, which is the clock input for the next flipflop.

Each T-flipflop divides its clock input frequency by two. Cascading them produces slower and slower frequency outputs. Note that here we clock each flipflop directly off the output of the preceeding flipflop, whereas in the lecture notes there is a NOT gate on the output. This is because the flipflops used here are trailing edge triggered, meaning that they change when the clock drops low. Most flipflops are leading edge triggered, meaning that they change when the clock goes high.

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Synchronous counter

This counter has the advantage that all the outputs change at the same time because all the flipflops are clocked from the same signal. Each T-flipflop is toggled only when all the lower bit flipflops are high.
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Sand box

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