computer science

OPENS DOORS


Research References in Opitcal Network on Chips

What the industry says/does in recent years

• “Intel turns to photonics to extend Moore's law”

• “Intel showcases 50 Gb/s silicon link”

• IBM: “Development of on-chip optical interconnects for future multi-core processors”

• “Alcatel-Lucent enters partnership for silicon photonics” • Luxtera: “Optics manufactured at wafer level”

• Kotura: “A worldwide leader in silicon photonics”

• Caliopa: UGent-IMEC start-up in silicon photonics

• “Cisco to acquire CMOS silicon photonics firm Lightwire”

• “Luxtera and STMicroelectronics to Enable High-Volume Silicon Photonics Solutions”

• Silicon Integrated Nanophotonic, http://researcher.ibm.com/researcher/view_project.php?id=2757; IBM Lights Up Silicon Chips to Tackle Big Data, http://www-03.ibm.com/press/us/en/pressrelease/39641.wss, Dec. 2012.

• Intel, Facebook Collaborate on Future Datacenter Rack Technologies, http://newsroom.intel.com/community /intel_newsroom/blog/2013/01/16/intel-facebook-collaborate-on-future-data-center-rack-technologies, Jan. 2013.

• Intel Silicon Photonics Demonstrated at 100 Gbps, http://newsroom.intel.com/community/intel_newsroom /blog/2013/04/11/chip-shot-intel-silicon-photonics-demonstrated-at-100-gbps, Apr.2013.

Marsden references

[1] Teraflops Research Chip, http://www.intel.com, 2011.

[2] 192-core CSX700 processor, http://www.clearspeed.com/products/csx700.php, 2012.

[3] International Technology Roadmap for Semiconductors (ITRS), http://www.itrs.net/.

[4] Silicon Integrated Nanophotonic; IBM Lights Up Silicon Chips Tackle Big Data, Dec. 2012. http://researcher.ibm.com/researcher/view_project.php?id=2757

http://www-03.ibm.com/press/us/en/pressrelease/39641.wss [5] Intel, Facebook Collaborate on Future Datacenter Rack Technologies, Jan. 2013.

http://newsroom.intel.com/community/intel_newsroom/blog/2013/01/16/intel-facebook- collaborate-on-future-data-center-rack-technologies [6] Intel Silicon Photonics Demonstrated at 100 Gbps, Apr.2013

http://newsroom.intel.com/community/intel_newsroom/blog/2013/04/11/chip-shot-intel-silicon- photonics-demonstrated-at-100-gbps

[7] Physicists Find Right (and Left) Solution for On-Chip Optics, Apr. 2013. http://www.sciencedaily.com/releases/2013/04/130422143313.html

[8] J. Lin, J. P. B. Mueller, Q. Wang, G. Yuan, N. Antoniou, X.-C. Yuan, F. Capasso. Polarization-Controlled Tunable Directional Coupling of Surface Plasmon Polaritons. Science, 2013.

[9] L. Feng, M. Ayache, J. Huang, Y. Xu, M Lu, Y. Chen, Y. Fainman, A. Scherer. Nonreciprocal Light Propagation in a Silicon Photonic Circuit, Science, 2011.

[10] D. Liang, J. Bowers. Recent progress in lasers on silicon. Nature Photonics, 2010.

[11] S. Assefa, F. Xia, Y. Vlasov. Reinventing Germanium Avalanche Photodetector for Nanophotonic on-chip optical interconnects, Nature, 2010.

[12] C. Batten, A. Joshi, V. Stojanovic, et al. Designing Chip-Level Nanophotonic Interconnection Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2012.

[13] D. Liang. Hybrid integrated platforms for silicon photonics, Materials, 2010.

[14] N. Lindenmann, G. Balthasar, D. Hillerkuss, R. Schmogrow, et al, Photonic Wire Bonding: A Novel Concept for Chip-scale Interconnects, Opt. Express 20, 2012.

[15] ITRS 2012 December Winter Meeting (Interconnect Group), http://www.itrs.net/Links/2012Winter/1205%20Presentation/Interconnect_12052012.pdf.

[16] Y. Ye, J. Xu, X. Wu, W. Liu, M. Nikdast. A Torus-based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip, ACM Journal on Emerging Technologies in Computing Systems, 2012.

[17] Z. Li, M. Mohamed, X. Chen, H. Zhou, A. Mickelson, L. Shang, M. Vachharajani, Iris: A Hybrid Nanophotonic Network Design for High-performance and Low-power on-chip Communication, ACM Journal on Emerging Technologies in Computing Systems, 2011.

[18] H. Gu, J. Xu, Z. Wang, Design of Sparse Mesh for Optical Network on Chip, in Proceedings of IEEE Asia Pacific Optical Communications (APOC), 2008.

[19] Y. Ye, J. Xu, and et al, 3D Mesh-based Optical Network-on-Chip for Multiprocessor System-on-Chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013.

[20] H. Gu, J. Xu, Design of 3D Optical Network on Chip, in Proceedings of International Symposium on Photonics and Optoelectronics (SOPO), 2009.

[21] H. Gu, J. Xu, W. Zhang, A Low-Power fat Tree-Based Optical Network-on-Chip for Multiprocessor System-on-Chip. Design, Automation and Test in Europe, 2009. (Citations: 72)

[22] H. Gu, S. Wang, Y. Yang, J. Xu, Design of Butterfly-Fat-Tree Optical Network-on-Chip, Optical Engineering, 2010.

[23] Z. Wang, J. Xu, X. Wu, Y. Ye, et al, Floorplan Optimization of Fat-Tree Based Networks-on-Chip for Chip Multiprocessors, IEEE Transactions on Computers, preprint, 2013.

[24] S. Beux, J. Trajkovic, I. Connor, G. Nicolescu, et al. Optical Ring Network-on-Chip (ORNoC): Architecture and Design Methodology. Design, Automation and Test in Europe (DATE), 2011.

[25] D. Vantrease, R. Schreiber, M. Monchiero, et al. Corona: System Implications of Emerging Nanophotonic Technology. International Symposium on Computer Architecture(ISCA), 2008.

[26] C. Batten, A. Joshi, V. Stojanovic, et al. Designing Chip-Level Nanophotonic Interconnection Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2012.

[27] S. Xiao, M. Khan, H. Shen, and M. Qi. Multiple-channel Silicon Micro-resonator based Filters for WDM applications. Optics Express, 2007.

[28] L. Bai, H. Gu, Y. Yang, X. Yu. A WDM Multi-waveguide Low Blocking Architecture for ONoC. Optics and Laser Technology, 2013.

[29] 4-wavelength Integrated Silicon Laser for Inter-processor Data Transmission, http://phys.org /news/2013-03-four-wavelength-silicon-laser-inter-processor-transmission.html, Mar. 2013.

[30] S. Beux, J. Trajkovic, I. O'Connor, G. Nicolescu, G. Bois, P. Paulin. Multi-Optical Network-on-Chip for Large Scale MPSoC. Embedded Systems Letters, 2010.

[31] G. Nychis, C. Fallin, T. Moscibroda, O. Mutlu, S. Seshan. On-chip Networks From a Networking Perspective: Congestion and Scalability in Many-core Interconnects. SIGCOMM, 2012.

[32] H. Li, H. Gu, Y. Yang, Z. Zhu, Impact of Thermal Effect on Reliability in Optical Network-on-Chip, Optik–International Journal for Light and Electron Optics, 2013.

[33] J. Chan, et al, Insertion Loss Analysis in a Photonic Interconnection Network for On-chip and Off-chip Communications, Meeting of the IEEE Lasers and Electro-Optics Society (LEOS), 2008.

[34] H. Gu, K. Mo, J. Xu, W. Zhang, A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip, in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2009. (Best Paper Honorable Mention Award)

[35] R. Ji, J. Xu, L. Yang, Five-Port Optical Router Based on Microring Switches for Photonic Networks-on-Chip, IEEE Photonics Technology Letters, 2013.

[36] Z. Chen, H. Gu, Y. Chen and H. Zhang. Source- and Destination-based Wavelength Assignment in Optical Network-on-Chip: Design and Performance. Technical Report (to submit to TENCON13), OUCS-2013-04, 2013.

[37] Z. Chen, H. Gu, Y. Yang, K. Chen. Low Latency and Energy Efficient Optical Network-on-chip Using Wavelength Assignment, IEEE Photonics Technology Letters, 2012. [IF: 2.19]

[38] I. Chlamtac, A. Ganz, and G. Karmi, Lightpath Communications: An Approach to High-Bandwidth Optical WAN’s, IEEE Transactions on Communications, 1992.

[39] OPNET Technologies Inc. (2010). Available online: http://www.opnet.com.

[40] S. Beux, I. O'Connor et al, Reduction Methods for adapting optical network on chip topologies to 3D architectures. Microprocessors and Microsystems - Embedded Hardware Design, 2013.

[41] K. H. Mo, Y. Ye, X. Wu, W. Zhang, W. Liu, J. Xu, A Hierarchical Hybrid Optical-electronic Network-on-chip, Proceedings of IEEE Computer Society Annual Symposium on VLSI, 2010.

[42] L. Bai, H. Gu, Y. Yang, K. Wang, A Crosstalk Aware Routing Algorithm for Benes ONoC, IEICE Electronics Express, 2012.

[43] R. W. Morris, et al, Power-efficient and High-performance Multi-level Hybrid Nanophotonic Interconnect for Multicores, ACM/IEEE International Symposium on Networks-on-Chip, 2010.

[44] M. Petracca et al. Design Exploration of Optical Interconnection Networks for Chip Multiprocessors, High Performance Interconnects (HOTI), 2008.

[45] S. Koohi, S. Hessabi, All-Optical Wavelength-Routed Architecture for a Power-Efficient Network on Chip, accepted for publication in IEEE Transactions on Computers, 2013.

[46] H. A. Khouzani, S. Koohi, et al, Fully Contention-free Optical NoC based on Wavelength Routing, International Symposium on Computer Architecture and Digital Systems (CADS), 2012.

[47] J. Zhang, H. Gu, Y. Yang. An Improved Distributed Routing Algorithm for Benes Based Optical NoC. Image Processing and Pattern Recognition in Industrial Engineering (IPPRIE), 2010.

[48] N. Kirman, J. F. Martinez, A Power-efficient All-optical On-chip Interconnect Using Wavelength-based Oblivious Routing, ACM SIGARCH Computer Architecture News, 2010.

[49] CPLEX Optimizer, http://www-01.ibm.com/software/commerce/optimization/cplex-optimizer/.

[50] Y. Chen, H. Shen, H. Zhang, Routing and Wavelength Assignment for Hypercube Communications Embedded on Optical Chordal Ring Networks of Degrees 3 and 4. Computer Communication, 2011.

[51] H. Zhang, H. Shen, Y. Chen, Z. Zhang, Balancing Energy Consumption for Data Gathering in Sensor Networks. 27th ACM Symposium on Principles of Distributed Computing (PODC), 2008.

[52] R. Liu, H. Gu, Y. Chen, H. Zhang. Analysing Packet-level Routing in Data Centers. Technical Report (submitted to IEEE Communication Letters), OUCS-2013-07, 2013. [53] K. Chen, H. Gu, Y. Chen, H. Zhang. TWC-based Approach for Improving Communication Reliability in ONoCs, Technical Report (submitted to ACFTCC13), OUCS-2013-06, 2013. [54] L. Bai, H. Gu, Y. Chen, et al. A Hierarchical Hybrid Optical-Electronic Clos architecture for ONoCs, Technical Report (submitted to Journal of lightwave technology), OUCS-2013-05, 2013.

Inter/Intra-Chip Optical Network Bibliography from other resources

link1 link2

architecture

Ye, Y., Xu, J., Wu, X., Zhang, W., Liu, W., and Nikdast, M. 2012. A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip. ACM J. Emerg. Technol. Comput. Syst. 8, 1, Article 5 (February 2012), 26 pages. [PDF]

Zhang, Lei, et al. "Architectures and routing schemes for optical network-on-chips." Computers and Electrical Engineering 35.6 (2009): 856-877. [PDF]

Johnnie Chan and Keren Bergman, "Photonic Interconnection Network Architectures Using Wavelength-Selective Spatial Routing for Chip-Scale Communications," J. Opt. Commun. Netw. 4, 189-201 (2012)

Mèlèk Channoufi et al, A novel optical network on chip design for future generation of multiprocessors system on chip, 2013.

Zhang, Lei, et al. "Architectures and routing schemes for optical network-on-chips." Computers and Electrical Engineering 35.6 (2009): 856-877.

Router Design

Yaoyao Ye, Xiaowen Wu, Jiang Xu, Wei Zhang, Mahdi Nikdast, Xuan Wang, “Holistic Comparison of Optical Routers for Chip Multiprocessors”, in Proceedings of IEEE International Conference on Anti-Counterfeiting, Security and Identification (ASID), Taipei, Taiwan, August 2012.

Ding, Duo, et al. "O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration." Proceedings of the 46th Annual Design Automation Conference. ACM, 2009.

Tan, Xianfang, et al. "A generic optical router design for photonic network-on-chips." Lightwave Technology, Journal of 30.3 (2012): 368-376.

Lee, Benjamin G., et al. "Multi-wavelength message routing in a non-blocking four-port bidirectional switch fabric for silicon photonic networks-on-chip." Optical Fiber Communication Conference. Optical Society of America, 2009.

Kirman, Nevin, and José F. Martínez. "A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing." ACM Sigplan Notices. Vol. 45. No. 3. ACM, 2010.

Survey

Michele Petracca, Keren Bergman, Luca P. Carloni: Photonic networks-on-chip: Opportunities and challenges. ISCAS 2008: 2789-2792. [PDF]

Haurylau, Mikhail, et al. "On-chip optical interconnect roadmap: challenges and critical directions." Selected Topics in Quantum Electronics, IEEE Journal of 12.6 (2006): 1699-1705. [PDF]

Carloni, Luca P., Partha Pande, and Yuan Xie. "Networks-on-chip in emerging interconnect paradigms: Advantages and challenges." Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip. IEEE Computer Society, 2009.

Floorplan desgn

Feng, Kai, Yaoyao Ye, and Jiang Xu. "A Formal Study on Topology and Floorplan Characteristics of Mesh and Torus-based Optical Networks-on-Chip." Microprocessors and Microsystems (2012).

Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Weichen Liu, Mahdi Nikdast: A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip. JETC 8(1): 5 (2012) [PDF]

Energy Issues

Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu: System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip. IEEE Trans. VLSI Syst. 21(2): 292-305 (2013)

A. Shacham, K. Bergman, and L. P. Carloni. Maximizing GFLOPS-per-Watt: High-bandwidth, low power photonic on-chip networks. In P=ac2 Conference, pages 12–21, Oct. 2006.

Wang, Zhehui, et al. "A novel low-waveguide-crossing floorplan for fat tree based optical networks-on-chip." Optical Interconnects Conference, 2012 IEEE. IEEE, 2012.

Koohi, Somayyeh, et al. "Energy Efficient All-Optical Arbitration in Optical Network-on-Chip." Optical Fiber Communication Conference. Optical Society of America, 2012.

contention-free

Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin: Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology. DATE 2011: 788-793 [PDF]

Somayyeh Koohi, Shaahin Hessabi: Scalable architecture for a contention-free optical network on-chip. J. Parallel Distrib. Comput. 72(11): 1493-1506 (2012) [PDF]

Somayyeh Koohi, Shaahin Hessabi, “All-Optical Wavelength-Routed Architecture for a Power-Efficient Network on Chip,” Accepted for publication in IEEE Transactions on Computers. [PDF]

Relaiblity

Wim Bogaerts,Pieter Dumon, Dries Van Thourhout, and Roel Baets. Low-loss, low-cross-talk crossings for silicon-on-insulator nanophotonic waveguides, Optics Letters, 2007. [PDF]

Good Slides

Presentation1

Silicon optical devices: on-chip laser sources [10–19], optical modulators [20–28], waveguides [20,29,30], and photodetectors [31-33]

[10] Fang AW, Koch BR, Gan K-G, Park H, Jones R, Cohen O, et al. A racetrack mode-locked silicon evanescent laser. Opt Exp 2008;16:1393–8.

[11] Iga K. Surface-emitting laser – its birth and generation of new optoelectronics field. IEEE J Select Top Quant Electron 2000;6:1201–15.

[12] Koch BR, Fang AW, Hsu-Hao C, Hyundai P, Ying-Hao K, Jones R, et al. A 40 GHz mode locked silicon evanescent laser. In: Presented at the 4th IEEE international conference on group IV photonics; 2007.

[13] Koch BR, Fang AW, Cohen O, Bowers JE. Mode-locked silicon evanescent lasers. Opt Exp 2007;15:11225–33.

[14] Liu J, Sun X, Camacho-Aguilera R, Kimerling CL, Michel J. Ge-on-Si laser operating at room temperature. Opt Lett 2010;35:679–81.

[15] Onishi Y, Saga N, Koyama K, Doi H, Ishizuka T, Yamada T, et al. Long-wavelength GaInNAs vertical-cavity surface-emitting laser with buried tunnel junction. IEEE J Select Top Quant Electron 2009;15:838–43.

[16] Rong H, Jones R, Liu A, Cohen O, Hak D, Fang A, et al. A continuous-wave Raman silicon laser. Nature 2005;433:725–8.

[17] Rong H, Liu A, Jones R, Cohen O, Hak D, Nicolaescu R, et al. An all-silicon Raman laser. Nature 2005;433:292–4.

[18] Rong H, Xu S, Kuo Y-H, Sih V, Cohen O, Raday O, et al. Low-threshold continuous-wave Raman silicon laser. Nat Photon 2007;1:232–7.

[19] Seassal C, Rojo-Romeo P, Letartre X, Viktorovitch P, Hollinger G, Jalaguier E, et al. InP microdisk lasers on silicon wafer: CW room temperature operation at 1.6 lm. Electron Lett 2001;37:222–3.

[20] Gu L, Jiang W, Chen X, Wang L, Chen RT. High-speed electro-optical silicon modulators based on photonic crystal waveguides. In: Presented at the silicon photonics II. Proceedings of the SPIE; 2007.

[21] Hemenway BR, Solgaard O, Bloom DM. All silicon integrated optical modulator for 1.3 lm fiber-optic interconnects. Appl Phys Lett 1989;55:349–50.

[22] Irace A, Breglio G, Cutolo A. All-silicon optoelectronic modulator with 1 GHz switching capability. Electron Lett 2003;39:232–3.

[23] Lipson M. Compact electro-optic modulators on a silicon chip. IEEE J Select Top Quant Electron 2006;12:1520–6.

[24] Liu A, Jones R, Liao L, Samara-Rubio D, Rubin D, Cohen O, et al. A high-speed silicon optical modulator based on a metal–oxide-semiconductor capacitor. Nature 2004;427:615–8.

[25] Liu A. Announcing the world’s first 40G silicon laser modulator; 2007. Available from: http://blogs.intel.com/research/.

[26] Liu A. Silicon photonic modulator transmits data at 30 Gb/s; 2007. Available from: http://blogs.intel.com/research/.

[27] Png CE, Chan SP, Lim ST, Reed GT. Optical phase modulators for MHz and GHz modulation in silicon-on-insulator (SOI). J Lightwave Technol 2004;22:1573–82.